1. Technical Field
The present invention relates generally to identifying defects in a semiconductor device, and more specifically relates to a logic diagnosis system and method that utilizes a table of manufacturing characterization data to isolate and identify design features known to be error prone.
2. Related Art
Given the complexities involved in manufacturing a semiconductor device, it is not uncommon for a device to have numerous operational faults in the early production stages. Identifying and analyzing these faults remains an important and costly challenge.
Traditional logic diagnosis relies on fault simulation software, which determines a set of logic nets (i.e., circuits) that are suspected to be at fault. Fault simulation software examines the logic of the faulty device, as well as logs of input and output values obtained from operating the actual device, and generates a list of suspect nets that might be causing the defect. From the suspect set of nets, a costly physical analysis is then implemented to attempt to link the defect to a particular physical location and/or manufacturing step. Unfortunately, the suspected set of nets often span across a large portion and various levels of the physical chip layout, thereby driving up the costs of the necessary physical analysis.
Accordingly, a need exists for a system that better diagnoses a failure by, e.g., narrowing down the set of suspected nets identified by today's fault simulation programs.